Course Name:
System Development and
Programming with the SHARC ADSP-21368/9,75
Course Description:
This is a practical course
with ‘hands on’ training using the latest software development tools.
The first section deals with getting a good working understanding of the VDSP++ development environment, including the development of a simple 'C' application. Next, the core elements of the SHARC, which includes the Computational
Units, the Data Address Generators, and the Program Sequencer, are examined
in detail along with the relevant assembly code instructions. The core
section is common to all members of the SHARC family. A number of simulator
labs help in understanding operation of the individual elements. Memory
configuration (both internal and external) is discussed next. Advanced
instructions are presented with a follow on lab on code optimization.
The I/O peripherals, which include the SPORTS, DAI, and DPI, are discussed
in detail along with DMA operation between these peripherals and internal
memory. This section also deals with system booting. Hardware development
tools, such as evaluation boards and ICE’s are introduced with a follow
on instructor led demonstrartion of an interrupt driven application
for a hardware target. Throughout the course, the various aspects of the
software development process using the latest tools are discussed including
setting up and building projects, 'C' and assembly language programming, code
debugging, simulation, VDK, and tool support for code overlays and shared memory. A detailed course outline can be found
at WS_2136x_OUT.PDF.
Course Objectives:
The main course
objective is to understand the SHARC architecture (with a focus on the
ADSP-21368/9, 75 Sharc Processor Family members) sufficiently to enable
DSP system designers to resolve hardware/software issues with their applications.
Additional goals include gaining a thorough understanding of SHARC code development (using both assembly
and 'C' ) using the latest software tools.
Who Should Attend:
System Designers
needing to make informed decisions on design tradeoffs, Hardware Designers
needing to develop external interfaces, and Code Developers needing to
know how to get the highest performance from their algorithms. Although
the focus of this workshop is on the ADSP-21368/9, 75, much of the workshop
is applicable to other members of the SHARC family as well.
Prerequisite:
Previous embedded
microprocessor experience (hardware and/or software) would be an asset.
Duration:
3.5 days
Course Fee:
Register early and save 6% on the workshop fee:
$1500 USD (North America) / $1850 USD (Europe) - If paid on or before the Run/Cancel Decision Date
$1595 USD (North America) / $1975 USD (Europe) - If paid after the Run/Cancel Decision Date
Schedule:
This workshop can also be provided at your facilities. Please
send your request to info@kaztek.com.
Workshop participants can get 50% off the regular price on their choice of any 3 Analog Devices hardware or software development tools.
Click here to ask for more details.
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